1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to methods for selectively inducing stress in the PMOS and NMOS transistors using a overlying stress inducing layer.
2) Description of the Prior Art
As semiconductor device speeds continue to increase and operating voltage levels continue to decrease, the performance of MOS and other types of transistors needs to be correspondingly improved. The carrier mobility in a MOS transistor has a significant impact on power consumption and switching performance, where improvement in carrier mobility allows faster switching speeds. The carrier mobility is a measure of the average speed of a carrier (e.g., holes or electrons) in a given semiconductor, given by the average drift velocity of the carrier per unit electric field. Improving carrier mobility can improve the switching speed of a MOS transistor, as well as allow operation at lower voltages.
One way of improving carrier mobility involves reducing the channel length and gate dielectric thickness in order to improve current drive and switching performance. However, this approach may increase gate tunneling current, which in turn degrades the performance of the device by increasing off state leakage. In addition, decreasing gate length generally calls for more complicated and costly lithography processing methods and systems.
Other attempts at improving carrier mobility include deposition of silicon/germanium alloy layers between upper and lower silicon layers under compressive stress, which enhances hole carrier mobility in a channel region. However, such buried silicon/germanium channel layer devices have shortcomings, including increased alloy scattering in the channel region that degrades electron mobility, a lack of favorable conduction band offset which may even mitigate the enhancement of electron mobility, and the need for large germanium concentrations to produce strain and thus enhanced mobility.
Thus, there remains a need for methods by which the carrier mobility of both NMOS and PMOS transistors may be improved, without significantly adding to the cost or complexity of the manufacturing process.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
Suey Li Toh, K. P. Loh, C. B. Boothroyd, K. Li, C. H. Ang, E. Er, and L. Chan; ARTICLE: Reduction of Local Mechanical Stress in a Transistor Using Si3N4 SiOxNy Contact ESL; Electrochemical and Solid-State Letters, 8 (2) G38-G40 (2005) 1099-0062/2004/8(2)/G38/3/$7.00© The Electrochemical Society, Inc. Found on website: www-hrem.msm.cam.ac.uk/˜cbb/publications/pdf/130%20Suey %20Li.pdf
U.S. Pat. No. 6,573,172: Methods for improving carrier mobility of PMOS and NMOS devices—Fabrication of semiconductor device by forming P-channel and N-channel metal oxide semiconductor transistors in wafer, forming tensile film on P-channel transistor and forming compressive film on N-channel transistor—Inventor: En, William George; Milpitas, Calif.
U.S. Pat. No. 6,284,610: Cha—Method to reduce compressive stress in the silicon substrate during silicidation—Silicidation of source/drain junctions in the manufacture of integrated circuit, involves depositing buffer oxide layer overlying semiconductor substrate and gate electrode.
US 20040159886 A1 Lee, Sang-Eun; et al.—Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby—
U.S. Pat. No. 6,348,389: Chou et al.—Method of forming and etching a resist protect oxide layer including end-point etch—Formation and etching of resist protect oxide layer, involves forming shallow trench isolation on semiconductor substrate, and depositing and etching the resist protect oxide layer using endpoint etch mode.
US20020142606A1—Yoon—Method for forming a borderless contact of a semiconductor device—A method for forming a borderless contact of a semiconductor device includes forming a gate electrode on a field oxide of the semiconductor substrate, patterning a stacked structure of a buffer layer and an etching barrier layer on sidewalls of the gate electrode and on the field oxide, forming a silicide layer on the gate electrode and an active region exposed by the stacked structure, and forming the borderless contacts to reduce or prevent leakage current between the semiconductor device and the metal lines and degradation resulting from stresses inherent in the prior art nitride etching barrier layer by reducing abnormal oxidation associated with the buffer oxide layer under the etching barrier layer.
U.S. Pat. No. 5,252,848—Adler—Low on resistance field effect transistor.